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Synopsys Jobs, Recruitment For Engineering Graduates Apply …

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R-SAT Exam (Recruitment Test)- To Get Short Listed ( 2013-2014 & 15 Freshers)

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Comapny Name : Synopsys

Job Title : R&D Engineer, Sr I

Location :INDIA – Bangalore

Experience : 5+ years

Requisition Number:7836BR

Job Category: Engineering

Job Description :
FPGA group in Synopsys delivers a number of products such as Synplify Pro, Synplify Premier, ProtoCompiler, Certify and Identify. These products are widely used in the industry for implementation of FPGA designs, prototyping and debugging of ASICs using FPGAs. Logic synthesis software, which is part of Synplify Pro and Synplify Premier products, is the industry standards for producing high-performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology® (BEST™) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, provides fast runtimes and support for very large designs.

Looking for a R&D engineer in Synplify mapper R&D team in Bangalore for the following role and with the given background/skill sets.

Roles and responsibility:

A person in the position would be responsible for designing, developing, troubleshooting, debugging and maintaining large and efficient software systems for technology mapping, logic and timing optimization steps of the FPGA logic synthesis software.
The person is expected to
Gather requirement and functional specifications, design and implement efficient data structures and algorithms in C/C++.
Work with CAE team in test planning, execution and customer support.
Maintain and support existing product and features.

Expected background and skill:
The person is expected to have:

B.Tech/M. Tech in CS/EE from a reputed institute.
5+ years of experience in designing, developing and maintaining large EDA software.
Sound knowledge in data structures, graph algorithms and C/C++ programming on Windows/Unix.
Familiarity in digital logic design.
Familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis.
Working knowledge of FPGA design tools and flows is a plus.

About Us :
Synopsys, Inc. (Nasdaq:SNPS) provides products and services that accelerate innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor intellectual property (IP), Synopsys’ comprehensive, integrated portfolio of solutions help address the key challenges designers face such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in quickly bringing the best products to market while reducing costs and schedule risk.

Founded by Dr. Aart de Geus and a team of engineers from General Electric’s Microelectronics Center in Research Triangle Park, North Carolina, Synopsys was first established as “Optimal Solutions” with a charter to develop and market ground-breaking synthesis technology developed by the team at General Electric. The company pioneered the commercial application of logic synthesis that has since been adopted by every major semiconductor design company in the world. This technology provided an exponential leap in integrated circuit (IC) design productivity by enabling engineers to specify chip functionality at a higher level of abstraction. Without this technology, the complex designs of today would not be possible.

Apply Here : 

Apply To Attend
R-SAT Exam (Recruitment Test)- To Get Short Listed ( 2013-2014 & 15 Freshers)

http://recruitercard.com/rsatschedule.htm

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